The present invention relates to a digital data processor and, more particularly, to a floating-point arithmetic processor (called hereinafter "FPP") in which an operation for exceptions is required.
An FPP performs high speed arithmetic operations such as ADD, SUBTRACT, MULTIPLY, DIVIDE, SQUARE ROOT, ROUND, etc., on one or more floating-point data, in place of a CPU (Central Processing Unit). Exceptional conditions such as Overflow and Underflow may arise during an arithmetic operation. Moreover, a SQUARE ROOT arithmetic operation calculating a square root of a negative number and a DIVIDE arithmetic operation performing a division by zero, i.e. Invalid-Operation and Division-by-zero exceptions may also occur. The FPP is thus required to perform an operation responsive to the occurrence of those exceptions.
According to the standard for floating-point arithmetic defined by IEEE, "ANSI/IEEE Std 754-1985", a MASK operation or TRAP operation is requested as the operation responsive to the occurrence of Overflow, Underflow, Invalid-Operation and Division-by-Zero exceptions. The MASK operation is to mask the occurrence of any exception. That is, even if the exception occurs, the FPP does not inform the CPU of the exception occurrence, so that the CPU continues to execute subsequent operations assuming no exception has occurred in the FPP. Since the exception has occurred in the FPP, however, the FPP writes a default value corresponding to the occurring exception into a destination register which may be accessed by the CPU to read data therefrom as a result of an arithmetic operation sent to the FPP. On the other hand, the TRAP operation is to supply an interruption request signal to the CPU when any exception occurs in the FPP. The CPU responds the interruption request signal thus supplied to suspend the execution of the subsequent operations and then to perform a processing operation for exceptions. Since the CPU performs the operation for exceptions, the content of the destination register should not be written with any default value to protect the destination register.
Thus, the MASK operation requires writing the default value into the destination register, whereas the TRAP operation requires protecting the current content of the destination register. Moreover, the MASK and TRAP operations should be designed to be selectable. For these reasons, the FPP according to prior art requires a complicated microprogram, so that high speed operation responsive to the occurrence of exceptions is not realized.